Wet etchant composition and method for etching HfO2 and ZrO2

ABSTRACT

A wet etchant solution composition and method for etching oxides of hafnium and zirconium including at least one solvent present at greater than about 50 weight percent with respect to an arbitrary volume of the wet etchant solution; at least one chelating agent present at about 0.1 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution; and, at least one halogen containing acid present from about 0.0001 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution.

FIELD OF THE INVENTION

The present invention relates generally to CMOS device fabricationprocesses and, more particularly, to a wet etchant composition andmethod for etching oxides of hafnium and zirconium.

BACKGROUND OF THE INVENTION

Fabrication of a metal-oxide-semiconductor (MOS) integrated circuitinvolves numerous processing steps. A gate dielectric, typically formedfrom silicon dioxide, is formed on a semiconductor substrate which isdoped with either n-type or p-type impurities. For each MOS field effecttransistor (MOSFET) being formed, a gate electrode is formed over thegate dielectric, and dopant impurities are introduced into the substrateto form source and drain regions. A pervasive trend in modern integratedcircuit manufacture is to produce transistors having feature sizes assmall as possible. Many modern day semiconductor microelectronicfabrication processes form features having less than 0.25 criticaldimensions, for example in future processes even less than 0.13 microns.As feature size decreases, the size of the resulting transistor as wellas transistor features also decrease. Fabrication of smaller transistorsallows more transistors to be placed on a single monolithic substrate,thereby allowing relatively large circuit systems to be incorporated ona single die area.

In semiconductor microelectronic device fabrication, polysilicon andsilicon dioxide (SiO₂) are commonly used to respectively form gateelectrodes and gate dielectrics for metal-oxide-semiconductor (MOS)transistors. As device dimensions have continued to scale down, thethickness of the SiO₂ gate dielectric layer has also decreased tomaintain the same capacitance between the gate and channel regions. Athickness of the gate oxide layer of less than 2 nanometers (nm) will berequired to meet smaller device design constraints. A problem with usingSiO₂ as the gate dielectric is that thin SiO₂ oxide films may break downwhen subjected to electric fields expected in some operatingenvironments, particularly for gate oxides less than about 50 Angstromsthick. In addition, electrons more readily pass through an insulatinggate dielectric as it gets thinner due to what is frequently referred toas the quantum mechanical tunneling effect. In this manner, a tunnelingcurrent, produces a leakage current passing through the gate dielectricbetween the semiconductor substrate and the gate electrode, increasinglyadversely affecting the operability of the device.

Because of high direct tunneling currents, SiO₂ films thinner than 1.5nm cannot be used as the gate dielectric in CMOS devices. There arecurrently intense efforts to replace SiO₂ with high-k (high dielectricconstant) dielectrics, including for example, TiO₂, Ta₂O₅, ZrO₂, Y₂O₃,La₂O₅, HfO₂, and their aluminates and silicates attracting the greatestattention. A higher dielectric constant gate dielectric allows a thickergate dielectric to be formed which dramatically reduces tunnelingcurrent and consequently gate leakage current, thereby overcoming asevere limitation in the use of SiO₂ as the gate dielectric. Whilesilicon dioxide (SiO₂) has a dielectric constant of approximately 4,other candidate high-k dielectrics have significantly higher dielectricconstant values of, for example, 20 or more. Using a high-k material fora gate dielectric allows a high capacitance to be achieved even with arelatively thick dielectric. Typical candidate high-k dielectric gateoxide materials have high dielectric constant in the range of about 20to 40.

There have been, however, difficulties in removing or etching certainhigh-k dielectric materials, particularly, oxides of hafnium andzirconium, for example hafnium dioxide and zirconium dioxide. Chemicaletchants used with high-k materials may cause damage to associated oxidematerials making high temperature rapid thermal oxidation (RTO)processes necessary to repair such damage which in turn may adverselyaffect the crystallinity or level of defects at the gatedielectric/silicon or silicon dioxide interface thereby degradingelectrical performance. For example, typically a shallow trenchisolation (STI) electrical isolation structure is formed adjacent a CMOSstructure to electrically isolate the various CMOS devices. A high-kdielectric layer is formed over the silicon substrate including the STItrench which has been previous backfilled with SiO₂. In a subsequentetching step to remove a portion of the high-k gate dielectricsurrounding the gate structure to reveal the silicon substrate, forexample to form a metal silicide layer, a high selectivity of etching ofthe high-k gate dielectric to SiO₂ is required to avoid etching the STIoxide which tends to form etching divots at the STI trench cornerregions thereby degrading electrical isolation performance. In addition,high-k dielectrics such as oxides of zirconium and hafnium areincreasingly advantageously used as etching stop layers due to theiretching resistance. Prior art processes for removing oxides of hafniumand zirconium have use sulfuric acid heated to temperatures of betweenabout 150° C. and about 180° C. The selectivity in the etching rate ofthe oxides of hafnium and zirconium, for example hafnium dioxide (HfO₂)and zirconium dioxide (ZrO₂), with respect to SiO₂, is about 0.6 toabout 1 with an etching rate of about 1 Angstrom/min. As a result,etching rates and selectivity to underlying SiO₂ layers for etching ofoxides of hafnium and zirconium is not optimal, successful etchingoperations optimally requiring higher etching rates and selectivity withrespect to SiO₂ thereby allowing reduced processing times and largerprocessing windows without the formation of etching divots. In addition,the added cost of implementing adequate environmental and safetyprotective measures for handling hot sulfuric acid as well as providingacid resistant processing tools is undesirable.

For example referring to FIG. 1A is shown a cross sectional view of aportion of a CMOS semiconductor device showing a STI trench 12A formedin silicon substrate 10 and backfilled with STI oxide 12B. Overlying theSTI oxide is a high-k dielectric material layer 14, for example hafniumdioxide or zirconium dioxide, formed for forming a gate dielectric in aCMOS device in an adjacent gate structure (not shown). Referring to FIG.1B according to prior art methods of etching the high-k dielectricmaterial layer, using, for example hot sulfuric acid, etching divotse.g., 16A and 16B are formed at the STI trench corner regions degradingdevice electrical isolation.

Therefore it would be advantageous to the semiconductormicro-fabrication processing art to develop a lower cost and moreeffective wet etching composition and method for etching high-kmaterials including oxides of hafnium and zirconium.

It is therefore an object of the invention to provide a lower cost andmore effective wet etching composition and method for etching high-kmaterials including oxides of hafnium and zirconium while overcomingother shortcomings and deficiencies of the prior art.

SUMMARY OF THE INVENTION

To achieve the foregoing and other objects, and in accordance with thepurposes of the present invention, as embodied and broadly describedherein, the present invention provides a wet etchant solutioncomposition and method for etching oxides of hafnium and zirconium.

In a first embodiment, the composition includes at least one solventpresent at greater than about 50 weight percent with respect to anarbitrary volume of the wet etchant solution; at least one chelatingagent present at about 0.1 weight percent to about 10 weight percentwith respect to an arbitrary volume of the wet etchant solution; and, atleast one halogen containing acid present from about 0.0001 weightpercent to about 10 weight percent with respect to an arbitrary volumeof the wet etchant solution.

In related embodiments, the wet etchant solution further includes atleast one surfactant present at about 0.1 weight percent to about 10weight percent with respect to an arbitrary volume of the wet etchantsolution.

In other related embodiments, the at least one solvent includes at leastone of H₂O, HClO₄, an alcohol, tetrahydrofuran (THF), sulfuric acid(H₂SO₄) and dimethyl sulfoxide (DMSO). Further, the at least onechelating agent is selected from the group consisting of diamines andbeta-diketones. Further yet, the at least one surfactant is selectedfrom the group consisting of polyols. Yet further, the at least onehalogen containing acid includes at least one of HF, HBr, HI, andH₃ClO₄.

In another aspect of the invention a method is provided for wet etchingoxides of hafnium and zirconium in a semiconductor micro-fabricationprocess including providing a material layer comprising an oxide of oneof at least one of hafnium and zirconium overlying a silicon dioxidecontaining material layer; and, wet etching the material layer with awet etching solution comprising at least a solvent and a halogencontaining acid formed to have a first etching rate with respect to thematerial layer that is at least about a factor of 2.5 greater than asecond etching rate with respect to the silicon dioxide.

These and other embodiments, aspects and features of the invention willbe better understood from a detailed-description of the preferredembodiments of the invention which are further described below inconjunction with the accompanying Figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a cross sectional side views of an exemplary STIstructure formed according to prior art wet etching processes.

FIGS. 2A and 2B are a cross sectional side views of an exemplary CMOSdevice formed according to an exemplary implementation of an embodimentof the wet etchant and wet etching method of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although the method and composition of the present invention isexplained with reference to the wet etching of oxides of hafnium andzirconium, it will be appreciated that the wet etching composition ofthe present invention may be used for the wet etching of any materialwhere wet etching may advantageously be performed in semiconductormicro-fabrication process having a comparable etching rate and aselectivity to SiO₂. In addition, although the method of the presentinvention is explained with reference to forming a gate structure, itwill be appreciated that the wet etchant composition of the presentinvention may be used in any semiconductor feature manufacturing processto selectively remove layers of material, for example an etch stoplayer, preferably including oxides of hafnium and zirconium, overlyingan SiO₂ containing material layer. The term “substrate” is defined tomean any semiconductive substrate material including conventionalsemiconductor wafers.

In a first embodiment according to the present invention a wet etchingcomposition for etching oxides of hafnium and zirconium, preferably atleast one of hafnium dioxide and zirconium dioxide is provided. In afirst embodiment, the wet etching composition comprises greater thanabout 50 wt % of one or more solvents, about 0 wt % to about 10 wt % ofone or more chelating agents, 0 wt % to about 10 wt % of one or moresurfactants and about 0.0001 wt. % to about 10 wt. % of one or morehalogen containing acids. It will be appreciated that the etching rateof oxides of hafnium and zirconium will depend in part on the manner offormation of the oxides and in part on the wet etchant compositionincluding the type of halogen containing acids, chelating agents, andsolvents. For example, the polarity of the solvents may affect the rateof molecular diffusion and the subsequent interaction of the chelatingagent or the acid with the etching target surface. In addition, it willbe appreciated that surfactants in some cases will aide the etchingaction by facilitating the interaction of the acid and chelating agentswith the targeted etching surface.

The solvents are preferably but not limited to at least one of H₂O,HClO₄, alcohol, including methyl, primary, secondary, tertiary, allyland benzyl alcohols, tetrahydrofuran (THF), Dimethyl sulfoxide (DMSO),sulfuric acid (H₂SO₄), and dimethyl sulfoxide (DMSO).

The chelating agents, if used, are preferably but not limited to atleast one of diamines, beta-diketones, and ethylene-diamine-tetra-aceticacid (EDTA). Other chelating agents that may suitably be used includeammonium salts including ammonium tartrate, ammonium citrate, ammoniumformate; ammonium glucomate; inorganic ammonium salts, such as ammoniumfluoride, ammonium nitrate, ammonium thiosulfate, ammonium persulfate,ammonium bicarbonate, ammonium phosphate, and the like. Exemplarydiamines include ethylene diamine, and2-methylene-amino-propylene-diamine. Other complexing agents may be usedas chelating agents to chelate oxides of hafnium and zirconium includetri- and polycarboxylic acids and salts with secondary or tertiaryhydroxyl groups in an alpha position relative to a carboxyl group suchas citric acid and citrates.

The surfactants, if used are preferably but not limited to at least onepolyols. Polyols are defined as structures with two OH groups onadjacent carbons, for example including glycol and glycerol otherwisereferred to as 1,2 propanediol and 1,2,3 propanetriol respectively. Thehalogen containing acids are preferably hydrogen fluoride (HF), hydrogenbromide (HBr), hydrogen iodide (HI), and H₃ClO₄. For example anexemplary wet etching composition includes about 10 wt % HF and about 90wt % ethanol. Another exemplary wet etching composition includes 10 wt %HF, 3 wt % glycol, 3 wt % EDTA, and about 84. wt % ethanol.

In an exemplary implementation of the wet etching composition of thepresent invention, referring to FIG. 2A is shown a cross sectional sideview of a portion of an exemplary CMOS transistor having a gatestructure 20 including a high-k gate dielectric layer 20A, preferablyincluding at least one of hafnium dioxide (HfO₂) and zirconium dioxide(ZrO₂) about 30 Angstroms to about 60 Angstroms in thickness, overlyingan optionally formed silicon dioxide (SiO₂) layer (not shown) about 5Angstroms to about 15 Angstroms in thickness. The gate dielectric 20A isformed overlying a semiconductor substrate 24, for example a siliconsubstrate including lightly doped regions e.g., 26A, and more heavilydoped source/drain regions, e.g., 26B. Shallow trench isolation (STI)regions, e.g., 28A and 28B surround the active area or channel region26C of the doped silicon substrate 24 to electrically isolate the gatestructure channel region from adjacent devices (not shown). The STItrenches are formed by conventional methods known in the art includingbeing backfilled with SiO₂, 28C also referred to as an STI oxide. Theregions 26A and 26B are typically formed following the formation of thegate structure by ion implantation and annealing processes known in theart.

Still referring to FIG. 2A, an electrically conductive gate electrode20B, for example polysilicon, is formed over the gate dielectric layer20A. The gate structure is formed by conventional deposition ofpolysilicon followed by a photolithographic and etching processes.Typically a first ion implantation process is then carried out to formthe LDD regions e.g., 26A and optionally dope the polysilicon electrodefor improved electrical conductivity. An oxide or nitride is thendeposited over the gate structure 20 followed by conventionalphotolithographic and etching processes to form sidewall spacers e.g.,22A and 22B on either side of the gate structure. The sidewall spacersare typically formed including for example at least one of silicon oxide(e.g., SiO₂), silicon oxynitride (e.g., SiON), and silicon nitride(e.g., SiN) including multiple layered spacers by methods known in theart including conventional deposition and etchback processes. A secondion implantation process is then carried out to form the more heavilydoped source/drain regions e.g., 26B in a self aligned ion implantationprocess where the sidewall spacers e.g., 22A act as an implantation maskto form N type or P type doping regions depending on whether a PMOS orNMOS type device is desired.

Referring to FIG. 2B, following the gate structure formation includingion implantation and annealing processes to form the doped regions inthe silicon substrate, a wet etching process using the wet etchingcomposition according to preferred embodiments of the present inventionis then used in a conventional wet etching process to remove selectedportions of the gate dielectric layer 20A surrounding the gate structure20. For example, the wet etching process preferably includes at leastone of an immersion process or a spraying process. For example, in animmersion or dipping process the semiconductor process wafer is dippedinto a wet etching solution for a period of time to substantially removethe gate dielectric layer on either side of the gate structure to exposethe silicon substrate. Preferably, the gate dielectric layer includes atleast one of hafnium dioxide and zirconium dioxide. If a thin SiO₂ layeris present underlying the gate dielectric layer and overlying thesilicon substrate, a second wet etching process may be used to removethe SiO₂ layer to reveal the silicon substrate. It will be appreciatedthat substantially complete removal of the gate dielectric layer 20A atselected portions of the process surface either side of the gatestructure 20 including any underlying oxide over the silicon substrateis required in order to successfully form a subsequent silicide orself-aligned silicide (salicide) contacts, for example a cobalt silicide(CoSi₂) or titanium silicide (TiSi₂), over the doped portions e.g., 26Bof the silicon substrate adjacent the gate structure and the upperportion of the polysilicon gate electrode 20B.

In an exemplary application using the wet etchant solution compositionaccording to preferred embodiments of the present invention the wetetchant solution is preferably maintained at a temperature of from about23° C. to about 60° C. Preferably the wet etchant solution is formulatedto have an etching rate of the gate dielectric layer with respect to thesilicon dioxide of about 2.5 or greater. Preferably the etching rate ofthe gate dielectric layer is greater than about 5 Angstroms per minute.

According to the wet etching composition of the present invention it hasbeen found that a gate dielectric layer including HfO₂ or ZrO₂ can beadvantageously etched with a high selectivity to SiO₂ for example,greater than about 2.5 with respect to a an SiO₂ etching rate. As such,etching divots into the edge portions of the STI trench oxide 28C areadvantageously avoided thereby improving electrical isolationperformance and reliability.

It will be appreciated that the wet etching composition of the presentinvention may advantageously be used in a variety of semiconductormicro-fabrication processes, for example where a high-k dielectricincluding oxides of hafnium and zirconium are used as etch stop layersand where the wet etching composition is advantageously used to removethe etch stop layer over a silicon oxide containing layer or structure,for example, an STI structure backfilled with STI oxide or aninter-metal dielectric (IMD) layer.

While the embodiments illustrated in the Figures and described above arepresently preferred, it should be understood that these embodiments areoffered by way of example only. The invention is not limited to aparticular embodiment, but extends to various modifications,combinations, and permutations as will occur to the ordinarily skilledartisan that nevertheless fall within the scope of the appended claims.

1. A wet etchant solution composition for etching oxides of hafnium andzirconium comprising: at least one solvent comprising greater than about50 weight percent with respect to an arbitrary volume of the wet etchantsolution; at least one chelating agent comprising from about 0.1 weightpercent to about 10 weight percent with respect to an arbitrary volumeof the wet etchant solution; and, at least one halogen containing acidcomprising from about 0.0001 weight percent to about 10 weight percentwith respect to an arbitrary volume of the wet etchant solution.
 2. Thewet etchant solution of claim 1, further comprising at least onesurfactant comprising from about 0.1 weight percent to about 10 weightpercent with respect to an arbitrary volume of the wet etchant solution.3. The wet etchant solution of claim 1, wherein the at least one solventincludes at least one of H₂O, HClO₄, an alcohol, tetrahydrofuran (THF),sulfuric acid (H₂SO₄) and dimethyl sulfoxide (DMSO).
 4. The wet etchantsolution of claim 1, wherein the at least one chelating agent isselected from the group consisting of diamines and beta-diketones. 5.The wet etchant solution of claim 2, wherein the at least one surfactantis selected from the group consisting of polyols.
 6. The wet etchantsolution of claim 5, wherein the surfactant comprises at least one ofglycol and glycerol.
 7. The wet etchant solution of claim 1, wherein theat least one halogen containing acid includes at least one of HF, HBr,HI, and, H₃ClO₄.
 8. A method for wet etching a material layer includingoxides of hafnium and zirconium in a semiconductor micro-fabricationprocess comprising the steps of: providing a material layer comprisingan oxide of at least one of hafnium and zirconium overlying a silicondioxide containing material layer; and, wet etching the material layerwith a wet etching solution comprising at least a solvent and a halogencontaining acid formed to have a first etching rate with respect to thematerial layer that is at least about a factor of 2.5 greater than asecond etching rate with respect to the silicon dioxide containingmaterial layer.
 9. The method of claim 8, wherein the material layercomprises at least one of hafnium dioxide (HfO₂) and zirconium dioxide(ZrO₂).
 10. The method of claim 9, wherein the solvent includes at leastone of H₂O, HClO₄, an alcohol, tetrahydrofuran (THF), sulfuric acid(H₂SO₄) and dimethyl sulfoxide (DMSO).
 11. The method of claim 10,wherein the solvent is present in the wet etchant solution at a weightpercent greater than about 50 weight percent with respect to anarbitrary volume of the wet etchant solution.
 12. The method of claim 9,wherein the halogen containing acid includes at least one of HF, HBr,HI, and H₃ClO₄.
 13. The method of claim 12, wherein the halogencontaining acid is present in the wet etchant solution from about 0.0001weight percent to about 10 weight percent with respect to an arbitraryvolume of the wet etchant solution.
 14. The method of claim 9, whereinthe wet etchant solution further comprises at least one surfactantselected from the group consisting of polyols comprising from about 0.1weight percent to about 10 weight percent with respect to an arbitraryvolume of the wet etchant solution.
 15. The method of claim 9, whereinthe wet etchant solution further comprises at least one chelating agentselected from the group consisting of diamines and beta-diketonescomprising from about 0.1 weight percent to about 10 weight percent withrespect to an arbitrary volume of the wet etchant solution.
 16. Themethod of claim 8, wherein the step of providing a material layercomprises providing a gate dielectric layer comprising at least one ofhafnium dioxide and zirconium dioxide.
 17. The method of claim 8,wherein the step of providing a material layer comprises providing anetching stop layer comprising at least one of hafnium dioxide andzirconium dioxide.
 18. The method of claim 9, wherein the step of wetetching comprises an etching rate of the material layer of greater thanabout 5 Angstroms per minute.
 19. The method of claim 8, wherein thestep of wet etching comprises the wet etchant solution maintained at atemperature of less than about 60° C.
 20. The method of claim 8, whereinthe step of wet etching comprises at least one of immersion andspraying.